1. Field of the Invention
This invention relates to a computer and, more particularly, to a bus interface unit having an accelerated graphics port ("AGP") compliant target which can be powered down to save power during times when an AGP master is not implementing master functions.
2. Description of the Related Art
Power consumption in an electronic device is always a significant concern. Longevity of the power supply, heat dissipation, physical size, weight, efficiency and other related characteristics are paramount in designing the electronic device. These characteristics become exceptionally critical when the device is a self-sufficient portable unit.
A portable unit is one in which power is supplied from a battery during times when the unit is decoupled from its main power source, e.g., a 110 volt ac supply. In some instances, the battery functions as an auxiliary power source to ensure critical circuits are kept alive and to retain information stored in memory. In other instances, the battery functions as the main power source to fully power the device in its operational state.
Various types of portable units can be powered from a battery including, for example, a computer. Modern portable computers are called upon to perform at increasingly higher levels. For example, a high performance portable computer may employ a high speed CPU and multiple buses between the CPU and numerous input/output devices. Multiple buses may include a CPU local bus connected directly to the CPU, a peripheral bus connected to slower input/output devices, and a mezzanine bus connected between the CPU local bus and the peripheral bus. In some instances, the mezzanine bus can be considered a peripheral bus, but typically operates at a higher speed than peripheral buses on which the slower input/output devices are connected. Thus, a truly peripheral bus can be classified as, for example, an industry standard architecture ("ISA") bus and enhanced ISA ("EISA") bus or a microchannel bus. The mezzanine bus, or faster peripheral bus, can be classified as, for example, a peripheral component interface ("PCI") bus.
Coupled between the various busses are bus interface units. According to somewhat known terminology, the bus interface unit coupled between the CPU bus and the PCI bus is often termed the "north bridge". Similarly, the bus interface unit between the PCI bus and the peripheral bus is often termed the "south bridge".
A bus interface unit configured as a north bridge can link, or "interface" more than simply the CPU bus and the PCI bus. In applications which are graphics intensive, a separate bus may be linked to the north bridge in addition to the CPU bus and the PCI bus. The additional bus linked to the north bridge can occur through what is known as the accelerated graphics port ("AGP"). AGP is generally known in the industry, and is well specified by Intel Corporation.
AGP is generally considered a high performance, component level interconnect targeted at three dimensional graphical display applications, and is based on a set of performance extensions or enhancements to PCI. AGP came about, in part, from the increasing demands placed on memory bandwidths for three dimensional renderings. AGP provided an order of magnitude bandwidth improvement between a graphics accelerator and system memory. This allowed some of the three dimensional rendering data structures to be effectively shifted into main memory, relieving the pressure to increase costs of memory local to the graphics accelerator or frame buffer.
AGP uses the PCI specification as an operational baseline, yet provides three significant performance extensions or enhancements to that specification. These extensions include a deeply pipelined read and write operation, demultiplexing of address and data on the AGP bus, and ac timing for faster, e.g., 133 MHz data transfer rates.
The AGP neither replaces or diminishes the necessity of PCI in the computer system. However, AGP is intended as an additional connection point to the north bridge, and can be used exclusively as an interface to visual display devices. All other devices or components may remain on the PCI bus.
Using conventional master/slave nomenclature, the graphics accelerator can be considered an AGP compliant master. The north bridge, and, specifically, the memory controller or core logic within the north bridge can be partially considered as an AGP compliant target. Accordingly, the AGP master is interchangeably deemed a graphics master which can issue AGP or graphics request to the AGP target. Associated with the AGP target is a PCI master which transfers PCI transactions to a PCI target embodied within the graphics master. Thus, the north bridge may comprise a dedicated graphics port which may receive requests from a graphics master to the graphics target within the north bridge. The graphics port may also transfer peripheral transactions from a peripheral masters within the north bridge to a peripheral target within the graphics master.
An arbiter is generally needed to arbitrate mastership of the graphics port and, specifically, the dedicated graphics bus. The arbiter arbitrates mastership of the graphics port between the graphics master and the peripheral master, both of which are coupled to the graphics port.
In situations in which the peripheral master does not have mastership of the graphics port, the graphics target nonetheless remains coupled to power. Thus, the graphics target and, specifically, the considerable sequential logic within that target consumes considerable power even though the graphics target is not called upon or needed for operation. The substantial size of the graphics target needed to service a graphics request presumes a substantial amount of power consumption within that target. An advantage would be achieved if the graphics target can be periodically disconnected from its clocking signal, or input buffers within the target disconnected from power, during times when the graphics target is not being requested. A need therefore exists for reducing power within a bus interface unit (e.g., north bridge) containing a graphics target, a peripheral master, and an arbiter. Reducing power within the graphics target and therefore within the north bridge would drastically reduce the major culprit of power consumption in the north bridge and therefore reduce the overall power consumption in a computer system.